1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (referred to hereinafter as an “IGBT”) for use in an inverter and the like.
2. Description of the Background Art
FIG. 7 is a schematic sectional view showing a structure of a first background art IGBT. As shown in FIG. 7, p doped regions 2 and 20 spaced a predetermined distance apart from each other are selectively formed in one main surface 100 of an n semiconductor layer 1 serving as an n type semiconductor substrate. N+ doped regions 3a and 3b spaced a predetermined distance apart from each other are selectively formed in a surface of the p doped region 2. Similarly, n+ doped regions 30a and 30b spaced a predetermined distance apart from each other are selectively formed in a surface of the p doped region 20.
An insulation film 40 is formed on part of the main surface 100 of the n semiconductor layer 1 which lies between the n+ doped regions 3b and 30a, and a gate electrode 50 is formed on the insulation film 40. An interlayer insulation film 70 is formed to cover the gate electrode 50. Similarly, an insulation film 41 is formed on part of the main surface 100 of the n semiconductor layer 1 which lies between the n+ doped region 3a and an n+ doped region not shown in FIG. 7, and a gate electrode 51 is formed on the insulation film 41. An interlayer insulation film 71 is formed to cover the gate electrode 51. An insulation film 42 is formed on part of the main surface 100 of the n semiconductor layer 1 which lies between the n+ doped region 30b and an n+ doped region not shown in FIG. 7, and a gate electrode 52 is formed on the insulation film 42. An interlayer insulation film 72 is formed to cover the gate electrode 52.
An emitter electrode 6 is formed on the main surface 100 of the n semiconductor layer 1 and on the interlayer insulation films 70 to 72. The emitter electrode 6 is connected to the n+ doped regions 3a, 3b, 30a, 30b and the p doped regions 2, 20.
An n+ buffer layer 8 having an impurity concentration higher than that of the n semiconductor layer 1 is formed on a main surface 101 of the n semiconductor layer 1 opposite from the main surface 100. A collector layer 90 which is a p+ semiconductor layer having a substantially uniform impurity concentration is formed on a main surface of the n+ buffer layer 8 opposite from the n semiconductor layer 1. A collector electrode 10 is formed on a main surface of the collector layer 90 opposite from the n+ buffer layer 8.
The first background art IGBT having the above-mentioned structure is disadvantageous in that a large number of holes injected from the collector layer 90 which is the p+ semiconductor layer in an off state make an off-state leakage current (referred to simply as a “leakage current” hereinafter) high at elevated temperatures. In general, the reduction in thickness of the n semiconductor layer 1 is very effective to improve characteristics, such as an on-state voltage and a turn-off power dissipation, of a high-breakdown-voltage IGBT. However, in reaction to the reduction in thickness of the n semiconductor layer 1, the current gain hFE of an internal pnp transistor increases in the off state to increase the leakage current. In particular, the first background art IGBT in which a large number of holes are injected from the collector layer 90 in the off state as discussed above presents a problem such that the reduction in thickness of the n semiconductor layer 1 significantly increases the leakage current. The “internal pnp transistor” in the first background art IGBT means a pnp bipolar transistor comprising the n semiconductor layer 1 and the n+ buffer layer 8 regarded as a base region, the p doped region 2 or the p doped region 20 regarded as a collector region, and the collector layer 90 regarded as an emitter region. The “off state” is a state in which, for example, the emitter electrode 6 and the gate electrodes 50 to 52 are placed at the same potential whereas a higher potential is applied to the collector electrode 10 than to the emitter electrode 6 and the gate electrodes 50 to 52, and in which the IGBT is off. The “leakage current” means a current flowing between the collector electrode 10 and the emitter electrode 6 in the off state.
To solve the above-mentioned problem, there has been proposed a second background art IGBT. FIG. 8 is a schematic sectional view showing a structure of the second background art IGBT. Although the collector layer 90 in the first background art IGBT is the p+ semiconductor layer having a substantially uniform impurity concentration, the second background art IGBT comprises a collector layer 91 in which collector short regions 120 which are n+ doped regions and p+ doped regions 92 alternate with each other.
More specifically, as shown in FIG. 8, the collector layer 91 has the collector short regions 120 and the p+ doped regions 92 which are formed alternately on the main surface of the n+ buffer layer 8 opposite from the n semiconductor layer 1. The collector electrode 10 is formed on a main surface of the collector layer 91 opposite from the n+ buffer layer 8. In other words, the collector electrode 10 is formed to cover the collector short regions 120 and the p+ doped regions 92. Such a structure is referred to as a “collector short structure.”
In the second background art IGBT having the above-mentioned structure, most electron currents leaked from the emitter electrode 6 side flow through the collector short regions 120 into the collector electrode 10 in the off state. This reduces the number of holes injected from the p+ doped regions 92. Therefore, the second background art IGBT can reduce the leakage current below that of the first background art IGBT, and alleviate the increase in leakage current resulting from the reduction in thickness of the n semiconductor layer 1.
There has been proposed a third background art IGBT different in structure from the second background art IGBT for reducing the leakage current below that of the first background art IGBT.
FIG. 9 is a schematic sectional view showing a structure of the third background art IGBT. Although the collector layer 90 in the first background art IGBT is the p+ semiconductor layer having a substantially uniform impurity concentration, the third background art IGBT comprises a collector layer 93 in which p+ doped regions 94 and p− doped regions 95 having an impurity concentration lower than that of the p+ doped regions 94 alternate with each other.
More specifically, as shown in FIG. 9, the collector layer 93 has the p+ doped regions 94 and the p− doped regions 95 which are formed alternately on the main surface of the n+ buffer layer 8 opposite from the n semiconductor layer 1. The collector electrode 10 is formed on a main surface of the collector layer 93 opposite from the n+ buffer layer 8. In other words, the collector electrode 10 is formed to cover the p+ doped regions 94 and the p− doped regions 95.
In the third background art IGBT having the above-mentioned structure, the total amount of impurity in the collector layer 93 is less than that in the collector layer 90 of the first background art IGBT. In the off state, the electron currents leaked from the emitter electrode 6 side are more easily flow through the p− doped regions 95 having a lower impurity concentration into the collector electrode 10. This reduces the number of holes injected from the collector layer 93. Therefore, the third background art IGBT can reduce the leakage current below that of the first background art IGBT, and alleviate the increase in leakage current resulting from the reduction in thickness of the n semiconductor layer 1, as compared with the first background art IGBT.
Unfortunately, the second background art IGBT configured to have the collector short structure includes a parasitic diode comprised of, for example, the p doped region 2, the n semiconductor layer 1, the n+ buffer layer 8 and the collector short regions 120. When used in an inverter and the like, the second background art IGBT is broken down in a freewheeling mode.
In the third background art IGBT, the electron currents flowing from the emitter electrode 6 side at turn-off flow rapidly through the p− doped regions 95 having a lower impurity concentration into the collector electrode 10. This rapidly decays the tail current in the collector current of the IGBT to reduce the turn-off power dissipation, but a collector-emitter voltage oscillates in some cases in timed relationship with the abrupt decay of the tail current. Thus, the third background art IGBT might malfunction or be broken down in the worst case.
There has been another problem such that the electron currents flowing from the emitter electrode 6 side while the IGBT is on are crowded in the IGBT to degrade the characteristics of the IGBT, depending on the position and number of regions easily conducting the electron currents in the collector layer, e.g. the collector short regions 120 in the second background art IGBT and the p− doped regions 95 in the third background art IGBT. FIG. 10 shows electron currents flowing in the second background art IGBT, and FIG. 11 shows electron currents flowing in the third background art IGBT.
As illustrated in FIG. 10, electron currents 300 from the emitter electrode 6 side while the IGBT is on flow toward the collector layer 91. Since the collector layer 91 has the collector short regions 120 which are the n+ doped regions, most of the electron currents 300 flow into the collector short regions 120. This gives rise to the crowding of the electron currents 300 in the second background art IGBT, depending on the position and number of collector short regions 120, as shown in FIG. 10. Hole currents 301 flowing in the IGBT are also shown in FIG. 10.
As illustrated in FIG. 11, the electron currents 300 from the emitter electrode 6 side while the IGBT is on flow toward the collector layer 93. Since the collector layer 93 has the partially formed p− doped regions 95 having a lower impurity concentration, most of the electron currents 300 flow into the p− doped regions 95. This gives rise to the crowding of the electron currents 300 in the third background art IGBT, depending on the position and number of p− doped regions 95, as shown in FIG. 11.